The present invention is generally related to comparison circuits and methods thereof. The present invention is also related to circuits that compare signals to capacitively stored voltage references. The present invention is additionally related to differential circuitry. The present invention is also related to circuits and techniques thereof for reducing the effect of power supply noise and reducing signal jitter. The present invention is additionally related to sensor jitter.
Circuits that compare a signal to a capacitively stored voltage reference, based on the value of the signal in the past, are generally impaired by changes in the power supply voltage, including noise. In such circuits the signal is a function of the power supply. The difference in the power supply voltage between the time an associated capacitor was initially charged, based on the past value of a signal, and the time the comparison to the present signal was accomplished provides an error that can register as signal jitter.
There are generally two types of jitter, commonly referred to as random jitter and deterministic jitter, the sum of which yields the total jitter at a specific reference plane in a communication system. Random jitter is the result of the random nature of noise sources within any non-ideal device. Sources of random noise include, but are not limited to, thermal, shot and flicker noise. Random noise sources add, root-mean-square-wise, to generally comprise the entire random jitter contribution of a system or subsystem. The predominant random noise source is a complex function of the system or subsystem implementation and the operational bandwidth.
Deterministic jitter results from systematic sources that by their nature can be xe2x80x9cdeterminedxe2x80x9d. Examples of deterministic jitter include, but are not limited to, duty cycle distortion, unequal rise and fall times for the devices used in the system""s implementation, dispersion due to interconnect media and distortion caused by the different frequencies that propagate through a transmission media at different phase velocities. Since high-frequency components of a signal are generally attenuated more than lower frequency components of the same signal, deterministic jitter tends to be prevalent in broad bandwidth systems.
A variety of techniques can be utilized to reduce jitter. Differential circuitry, for example, typically provides sufficient immunity to common mode and power supply noise. Once the signal is converted to a single-ended signal to compare against a capacitively-stored reference, however, this immunity is often lost.
Based on the foregoing, the present inventors have concluded that a need exits for a reliable and efficient circuit and technique thereof for reducing signal jitter and canceling the first order effects of power supply noise, particularly in configurations in which signals are compared to capacitively-stored reference voltages. The present inventors believe the circuit described herein, including a method for forming such a circuit, addresses these needs.
The following summary of the invention is provided to facilitate an understanding of some of the innovative features unique to the present invention, and is not intended to be a full description. A full appreciation of the various aspects of the invention can be gained by taking the entire specification, claims, drawings, and abstract as a whole.
It is, therefore, one aspect of the present invention to provide an improved comparison circuit for comparing signals to capacitively stored voltage references.
It is another aspect of the present invention to provide a power supply rejection circuit for capacitively-stored reference voltages.
It is yet another aspect of the present invention to provide a power supply rejection circuit in which a cancellation of power supply noise results.
It is still another aspect of the present invention to provide a power supply rejection circuit that forces differences in supply voltage to appear on a capacitor reference voltage.
It is also an aspect of the present invention to provide a power supply rejection circuit, which reduces the effect of power supply noise when comparing a signal to a capacitively-stored reference.
It is additionally an aspect of the present invention to provide a power supply rejection circuit that may be adapted for use with a sensor.
The above and other aspects can be achieved as is now described. A power supply rejection circuit and method thereof for capacitively-stored reference voltages is disclosed herein. The power supply rejection circuit generally comprises a comparison circuit for comparing a signal associated with a power supply to a stored reference voltage, such that the comparison circuit includes at least one existing capacitor therein. At least one additional capacitor can be then coupled to the comparison circuit such that the additional capacitor creates a capacitively coupled voltage divider in parallel with the stored reference voltage. This capacitor voltage divider can thus negate the first order effects of power supply noise in the system. Utilizing an additional capacitor in this manner can thus significantly reduce and/or eliminate the effect of power supply noise.
The additional capacitor generally comprises a first end and a second end. The first end of the additional capacitor is generally connected to the existing capacitor of the comparison circuit. The second end of the additional capacitor can also be connected to the supply voltage. In this manner, the additional capacitor comprises a capacitor from the supply voltage to a stored reference point associated with the power supply rejection circuit.
The existing capacitor generally comprises a second capacitor from the stored reference voltage to a ground. The additional capacitor and the existing capacitor together effectively operate in parallel with one another. The additional capacitor connected to the comparison circuit forces a percentage of the differences in supply voltage to appear on the stored reference voltage, thereby ensuring that the stored reference voltage is adjusted an equal amount by which a present single-ended output signal from the comparison circuit is offset. The percentage can thus be determined by a ratio of capacitors.
The present invention thus reduces the effect of power supply noise when comparing a single-ended signal to a capacitively-stored reference. This is accomplished by forcing differences in supply voltage to appear on a capacitor reference voltage. In this manner, the capacitively-stored reference voltage can be adjusted the same amount by which a present single-ended output signal is offset. This technique provides a cancellation of power supply noise (i.e., differences over time) and improves signal jitter.
The present invention thus provides an improvement by adding at least one capacitor to the comparison circuit. One end of the added capacitor can be added to the existing capacitor, which stores the reference voltage. The other end of the added capacitor can be connected to the supply voltage (i.e., versus ground for the other capacitor). The end result is a capacitor from the supply to the stored reference point and a capacitor from the stored reference signal to ground (i.e., existing cap).